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p reliminary w987x6cb 2m 4 banks 16 bit sdram publication release date: june 6, 2002 - 1 - revision a 1 table of contents - 1. general descripti on ................................ ................................ ................................ .................. 3 2. features ................................ ................................ ................................ ................................ .......... 3 3. available part nu mber ................................ ................................ ................................ .............. 3 4. ball configuratio n ................................ ................................ ................................ ..................... 4 5. ball description ................................ ................................ ................................ ........................... 5 6. block diagram ................................ ................................ ................................ ............................... 6 7. absolute maximum ratings ................................ ................................ ................................ ...... 7 8. dc electrical cha racteristics and ope rating conditions ................................ ....... 7 9. capacitance ................................ ................................ ................................ ................................ ... 7 10. operating curren t ................................ ................................ ................................ ................... 8 11. ac characteristi cs and operating con dition ................................ ............................... 9 12. functional descr iption ................................ ................................ ................................ ........ 12 power up sequence ................................ ................................ ................................ ....................... 1 2 command function ................................ ................................ ................................ ........................ 12 read operation ................................ ................................ ................................ .............................. 15 write operation ................................ ................................ ................................ ............................... 15 precharge ................................ ................................ ................................ ................................ ....... 15 burst termination ................................ ................................ ................................ ........................... 15 interruption ................................ ................................ ................................ ................................ ...... 16 refresh operation ................................ ................................ ................................ .......................... 16 power down mode ................................ ................................ ................................ ......................... 17 mode register set operation ................................ ................................ ................................ ......... 17 simplified state diagram ................................ ................................ ................................ ................ 19 13. timing waveforms ................................ ................................ ................................ .................... 20 command input timing ................................ ................................ ................................ .................. 20 read timing ................................ ................................ ................................ ................................ ... 21 control timing of input/output data ................................ ................................ ............................... 22 14. operating timing example ................................ ................................ ................................ .... 24 interleaved bank read (burst length = 4, cas late ncy = 3) ................................ ........................ 24 interleaved bank read (burst length = 4, cas latency = 3, auto precharge) ............................. 25 interleaved bank read (burst length = 8, ca s latency = 3) ................................ ........................ 26
p reliminary w987x6cb - 2 - interleaved bank read (burst length = 8, cas latency = 3, auto precharge) ............................. 27 interleaved bank write (burst lengt h = 8) ................................ ................................ ..................... 28 interleaved bank write (burst length = 8, auto precharge) ................................ .......................... 29 page mode read (burst length = 4, cas latency = 3) ................................ ................................ 30 page mode read/write (burst length = 8, cas latency = 3) ................................ ....................... 31 auto precharge read (burst length = 4, cas latency = 3) ................................ .......................... 32 auto precharge write (burst length = 4) ................................ ................................ ....................... 33 auto refresh cycle ................................ ................................ ................................ ......................... 34 self refresh cycle ................................ ................................ ................................ .......................... 35 burst read and single write (burst length = 4, cas latency = 3) ................................ ............... 36 power down mode ................................ ................................ ................................ ......................... 37 auto precharge timing (read cycle) ................................ ................................ ............................. 38 auto precharge timing (write cycle) ................................ ................................ ............................. 39 timing chart of read to write cycle ................................ ................................ .............................. 40 timing chart of write to read cycle ................................ ................................ .............................. 40 timing chart of burst stop cycle (burst stop command) ................................ ............................. 41 timing chart of burst stop cycle (precharge command) ................................ ............................. 41 cke/dqm input timing (write cycle) ................................ ................................ ............................ 42 cke/dqm input t iming (read cycle) ................................ ................................ ............................ 43 self refresh/power down mode exit timing ................................ ................................ .................. 44 15. package dimensio n ................................ ................................ ................................ .................. 45 16. revision history ................................ ................................ ................................ ....................... 46
p relim inary w987x6cb publication release date: june 6, 2002 - 3 - revision a 1 1. general descripti on w987x6cb is a high - speed synchronous dynamic random access memory (sdram), organized as 2m words 4 banks 16 bits. using pipelined architecture and 0.17 5 m m process technology, w987x6cb delivers a data bandwidth of up to 125m words per second ( - 8). for different application, w987x6cb is sorted into two speed grades: - 75 and - 8 . the - 75 is compliant to the 1 33 mhz/cl3 specification; the - 8 is compliant to the 1 25 mhz/cl3 specification. for handheld device application, these parts are specially designed with several power saving mechanisms to achieve extremely low self refresh current. accesses to the sdram are burst oriented. consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an active command. column addresses are automatically generated by the sdram internal counter in burst operation. random column read is also possible b y providing its address at each clock cycle. the multiple bank nature enables interleaving among internal banks to hide the precharging time. by having a programmable mode register, the system can change burst length, latency cycle, interleave or sequentia l burst to maximize its performance. w987x6cb is ideal for main memory in high performance applications. 2. features power supply v dd = 2.5v 0.2v v ddq = 1.8v standard self refresh mode power down mode cas latency: 2 and 3 burst length: 1, 2, 4, 8, and full page 4k refresh cycles / 64 ms interface: lvttl packaged in 54 balls fbga, operating temperature range commercial temperature (0 c - 70 c) industrial temperature ( - 40 c - 85 c) 3. available part nu mber part number speed s elf refresh current (max.) temperature range lead - free package w987x6cbn75 1 33 mhz/cl3 400 m a 0 c - 70 c no W987X6CBG75 1 33 mhz/cl3 400 m a 0 c - 70 c yes w987x6cbn80 1 25 mhz/cl3 400 m a 0 c - 70 c no w987x6cbg80 1 25 mhz/cl3 400 m a 0 c - 70 c yes
p reliminary w987x6cb - 4 - 4. ball configuratio n 1 2 3 4 5 6 7 8 9 a b c d e f g h j (top view) v dd dq7 dq1 dq3 dq5 we cs a10/ ap v dd vss dq8 dq14 dq12 dq10 udqm nc a8 vss dq0 ldqm dq2 dq4 dq6 ras ba1 a1 a2 dq15 nc dq13 dq11 dq9 clk a11 a7 a5 v dd q v dd cas ba0 a0 a3 v ss q v dd q v ss q v ss q v ss v dd q v ss q v dd q cke a9 a6 a4 package dimension 8 mm x 9 mm
p relim inary w987x6cb publication release date: june 6, 2002 - 5 - revision a 1 5. ball description pin number ball name function description h7, h8, j8, j7, j3, j2, h3, h2, h1, g3, h9, g2 a0 - a11 address multiplexed pins for row and column address . row address: a0 - a11. column address: a0 - a8. g7, g8 bs0, bs1 bank select select bank to activate during row address latch time, or bank to read/write during address latch time. a8, b9, b8, c9, c8, d9, d8, e9, e1, d2 d1, c2, c1, b2, b1, a2 dq0 - dq1 5 data input/ output multiplexed pins for data output and input. g9 cs chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. f8 ras row address strobe command input. when sampled at the rising edge of the clock, ras , cas and we define the operation to be executed. f7 cas column address strobe refe rred to ras f9 we write enable referred to ras f1, e8 udqm ldqm input/output mask the output buffer is placed at hi - z (with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency. f2 clk clock inputs system clock used to sample inputs on the rising edge of clock. f3 cke clock enable cke controls the clock activation and deactivation. when cke is low, power down m ode, suspend mode or self refresh mode is entered. a9, e7, j9 v dd power power for input buffers and logic circuit inside dram. a1, e3, j1 v ss ground ground for input buffers and logic circuit inside dram. a7, b3, c7, d3 v ddq power for i/o buffer separa ted power from v cc , used for output buffers to improve noise. a3, b7, c3, d7 v ssq ground for i/o buffer separated ground from v ss , used for output buffers to improve noise. e2, g1 nc no connection no connection
p reliminary w987x6cb - 6 - 6. block diagram dq0 dq15 udqm ldqm clk cke cs ras cas we a10 a0 a9 a11 bs0 bs1 clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 4096 * 512 * 16. dmn r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r
p reliminary w987x6cb publication release date: june 6, 2002 - 7 - revision a 1 7. absolute maximum ratings parameter symbol rating unit note input/output voltage v in , v out - 0.3 - v dd +0.3 v 1 power supply voltage v dd , v ddq - 0.3 - 3.6 v 1 operating temperature (commercial parts) t opr 0 - 70 c 1 operating temperature (ind ustrial parts) t opr - 40 - 85 c 1 storage temperature t stg - 55 - 150 c 1 soldering temperature (10s) t solder 260 c 1 power dissipation p d 1 w 1 short circuit output current i out 50 ma 1 8. dc electrical cha racteristics and ope rating conditions (t a = 0 c to 70 c for commercial parts, t a = - 40 c to 85 c for industrial parts) parameter symbol min. typ. max. unit supply voltage v dd 2.3 2.5 2.7 v supply voltage (for i/o buffer) v ddq 1.65 1.8 1.95 v input high level voltage v ih 0.8 * v ddq - v ddq + 0 .3 v input low level voltage v il - 0.3 - 0.2 * v ddq v lvttl output 2 h 2 level voltage (i out = - 0.1 ma ) v oh v ddq - 0.2 - - v lvttl output 2 l 2 level voltage (i out = +0.1 ma ) v ol - - 0.2 v input leakage current (0v v in v dd , all other pins not under tes t = 0v) i i(l) - 5 - 5 m a output leakage current (output disable , 0v v out v ccq ) i o(l) - 5 - 5 m a note: v ih (max) = v dd / v ddq +1.2v for pulse width < 5 ns v il (min) = v ss / v ssq - 1.2v for pulse width < 5 ns 9. capacitance (v dd = 2.5v, f = 1 mhz, t a = 25 c ) parameter symbol min. max. unit input capacitance (a0 to a11, bs0, bs1, cs , ras , cas , we , dqm, cke) c i - 3.8 pf input capacitance (clk) c clk - 3.5 pf input/output capacitance c io - 6.5 pf note : these parameters are periodically sampled and not 100% tested.
p reliminary w987x6cb - 8 - 10. operating curren t (v dd = 2.5v 0.2v, t a = 0 c to 70 c for commercial parts ,t a = - 40 c to 85 c for industrial parts) - 75/75i - 8/ - 8i parameter sym. max. max. unit notes o perating current t ck = min., t rc = min. active precharge command cycling without burst operation 1 bank operation i cc1 65 60 3 standby current t ck = min, cs = v ih cke = v ih i cc2 15 15 3 v ih / l = v ih (min.)/ v il (max.) bank: inactive sta te cke = v il (power down mode) i cc2p 0.5 0.5 3 standby current clk = v il , cs = v ih cke = v ih i cc2s 10 10 v ih / l = v ih (min.)/ v il (max.) bank: inactive state cke = v il (power down mode) i cc2ps 0.35 0.35 ma no operating current t ck = m in., cs = v ih (min.) cke = v ih icc3 20 20 bank: active state (4 banks) cke = v il (power down mode) icc3p 2 2 burst operating current t ck = min. read/ write command cycling icc4 90 85 3, 4 auto refresh current t ck = min. auto refresh command cycling icc5 150 140 3 self refresh current self refresh mode cke = 0.2v i cc6 400 400 m a deep power down mode current icc7 10 10 m a
p relim inary w987x6cb publication release date: june 6, 2002 - 9 - revision a 1 11. ac characteristi cs and operating con dition (vcc = 2.5v 0.2v, t a = 0 c to 70 c for commercial parts ,t a = - 40 c to 85 c for industrial parts; notes: 5, 6, 7, 8) - 75 / 75 i - 8/ - 8i parameter sym. min. max. min. max. unit ref/active to ref/active command period t rc 65 68 active to precharge command period t ras 45 100000 48 100000 ns active to read/wr ite command delay time t rcd 20 20 read/write(a) to read/write(b)command period t ccd 1 1 cycle precharge to active command period t rp 20 20 active(a) to active(b) command period t rrd 15 16 cl* = 2 10 10 write recovery time cl* = 3 t wr 7 .5 8 cl* = 2 10 10 clk cycle time cl* = 3 t ck 7.5 8 clk high level width t ch 2.5 3 clk low level width t cl 2.5 3 cl* = 2 6 6 access time from clk cl* = 3 t ac 5.4 6 ns output data hold time t oh 3 3 output data high impedan ce time t hz 3 7.5 3 8 output data low impedance time t lz 0 0 power down mode entry time t sb 0 7.5 0 8 transition time of clk (rise and fall) t t 0.3 10 0.3 10 data - in set - up time t ds 1.5 2 data - in hold time t dh 1 1 address set - up time t as 1.5 2 address hold time t ah 1 1 cke set - up time t cks 1.5 2 cke hold time t ckh 1 1 command set - up time t cms 1.5 2 command hold time t cmh 1 1 refresh time t ref 64 64 ms mode register set cycle time t rsc 15 16 ns *cl = cas laten cy
p reliminary w987x6cb - 10 - n otes: 1. operation exceeds "absolute maximum rating" may adversely affect the life and reliability of the devices. 2. all voltages are referenced to v ss 3. these parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum val ues of t ck and t rc . 4. these parameters depend on the output loading conditions. specified values are obtained with output open. 5. power up sequence is further described in the "functional description" section. 6. ac testing conditions output reference level 0.5 * v ddq output load see diagram below input signal levels 0.8* v ddq / 0.2* v ddq transition time (rise and fall) of input signal 1 ns input reference level 0.5 * v ddq 50 ohms ac test load z = 50 ohms output 30pf 0.5 x v dd q 7. transition times are measured between v ih and v il . 8. t hz defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 9. the value that shown on table are based on silicon simulation result. it will be changed according to real product characteristic.
p relim inary w987x6cb publication release date: june 6, 2002 - 11 - revision a 1 operati on mode fully synchronous operations are performed to latch the commands at the positive edges of clk. table 1 shows the truth table for the operation commands. table 1 truth table (note (1), (2)) command device state cken - 1 cken dqm bs0, 1 a10 a0 - a9 a11 cs ras cas we bank active idle h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) h x x v l v l h l l wri te with autoprecharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read with autoprecharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no ? operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x auto ? refresh idle h h x x x x l l l h self - refresh entry idle h l x x x x l l l h self refresh exit idle (s.r.) l l h h x x x x x x x x h l x h x h x x clock suspend entry active h l x x x x x x x x power down entry idle active (5) h h l l x x x x x x x x h l x h x h x x clock suspend exit active l h x x x x x x x x power down exit any (power down) l l h h x x x x x x x x h l x h x h x x deep power down entry idle h l x x x x l h h l de ep power down exit dpdm l h x x x x x x x x data write/output enable active h x l x x x x x x x data write/output disable active h x h x x x x x x x notes: 1. v = valid x = don't care l = low level h = high level 2. cken signal is input level when comman ds are provided. cken - 1 signal is the input level one clock cycle before the command is issued. 3. these are state of bank designated by bs0, bs1 signals. 4. device state is full page burst operation.
p reliminary w987x6cb - 12 - 5. power down mode can not be entered in the burst cycle. when t his command asserts in the burst cycle, device state is clock suspend mode. 12. functional descr iption power up sequence the default power up state of the mode register is unspecified. the following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. during power up, all v dd and v ddq pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "nop" state. the power up voltage must not excee d v dd +0.3v on any of the input pins or v dd supplies. after power up, an initial pause of 200 m s is required followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power up, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. an additional eight auto refresh cycles (cbr) are also required before or aft er programming the mode register to ensure proper subsequent operation. command function bank activate command ( ras = " l " , cas = " h " , we = " h " , bs0, bs1 = bank, a0 to a11 = row address) the bank ac tivate command activates the bank designated by the bs (bank select ) signal. row addresses are latched on a0 to a11 when this command is issued and the cell data is read out of the sense amplifiers. the maximum time that each bank can be held in the active state is specified as t ras (max) . after this command is issued, read or write operation can be executed. bank precharge command ( ras = " l " , cas = " h " , we = " l " , bs0, bs1 = bank, a10= " l " , a0 to a9, a11 = don?t care) the bank precharge command percharges the bank designated by bs. the precharged bank is switched from the active state to the idle state. precharge all command ( ras = " l " , cas = " h " , we = " l " , bs0, bs1 = don?t care, a10= " h " , a0 to a9, a11 = don?t care) the precharge all command precharges all banks simultaneously. then all banks are switched to the idle state. write command ( ras = " h " , cas = " l " , we = " l " , bs0, bs1 = bank, a10 = " l " , a0 to a 8 = column address) the write command performs a write operation to the bank designated by bs. the write data are latched at rising edge of clk. the length of the write data (burst leng th) and column access sequence (addressing mode) must be programmed in the mode register at power - up prior to the write operation.
p relim inary w987x6cb publication release date: june 6, 2002 - 13 - revision a 1 write with auto precharge command ( ras = " h " , cas = " l " , we = " l " , bs0, bs1 = bank, a10 = " h " , a0 to a 8 = column address) the write with auto precharge command performs the precharge operation automatically after the write operation. this command must not be interrupted by any other commands. read command ( ras = " h " , cas = " l " , we = " h " , bs0, bs1 = bank, a10 = " l " , a0 to a 8 = column address) the read command performs a read operation to the bank designated by bs. the length of read data (burst length), addressing mo de and cas latency (access time from cas command in a clock cycle) must be programmed in the mode register at power - up prior to the read operation. read with auto precharge command ( ras = " h " , cas = " l " , we = " h " , bs0, bs1 = bank, a10 = " h " , a0 to a 8 = column address) the read with auto precharge command automatically performs the precharge operation after the read operation. this command must not be interrupted by any other command. mode register set command ( ras = " l " , cas = " l " , we = " l " , bs0= " l " , bs1= " l " , a0 to a11 = register data) the mode register set command programs the values of burst length, add ressing mode, cas latency and write mode in the mode register. the default values in the mode register after power - up are undefined, therefore this command must be issued during the power - up sequence. also, this command can be issued wh ile all banks are in the idle state. refer to the table for specific codes. extended mode register set command ( ras = " l " , cas = " l " , we = ?l " , bs0= " l " , bs1 = " h " , a0 to a11 = register data) the ex tended mode register set command programs the values of driver strength, temperature compensated self refresh and partial array self refresh. the default value of the extended mode register is full driver strength, 70 degrees c and all banks refreshed no - o peration command ( ras = " h " , cas = " h " , we = " h " ) the no - operation command simply performs no operation (same command as device deselect). burst read stop command ( ras = " h " , cas = " h " , we = " l " ) the burst stop command is used to stop the burst operation. this command is only valid during a burst read operation.
p reliminary w987x6cb - 14 - device deselect command ( cs = " h " ) the device deselect command disables the command decoder so that the ras , cas , we and address inputs are ignored. this command is similar to the no - operation command. auto refresh command ( ras = " l " , cas = " l " , we = " h " , cke = " h " , bs0, bs1, a0 to a11 = don?t care) the auto refresh command is used to refresh the row address provided by the internal refresh counter. the refresh operation must be performed 4096 times with in 64ms. the next command can be issued after t rc from the end of the auto refresh command. when the auto refresh command is used, all banks must be in the idle state. self refresh entry command ( ras = " l " , cas = " l " , we = " h " , cke = " l " , bs0, bs1, a0 to a11 = don?t care) the self refresh entry command is used to enter self refresh mode. while the device is in self refresh mode, all input and output buffer (except the cke buffer) are disabled and the refresh operation is automatically performed. self refresh mode is exited by taking cke ?high? (the self refresh exit command). self refresh exit command (cke= " h " during sdram in self refresh mode) this command is used to exit from self refresh mode. any subsequent commands can be issued after t rc from the end of this command. deep power down mode entry command ( ras = " h " , cas = " h " , we = " l " , cke= " l " , bs0, bs1, a0 to a11 = don?t care) the deep po wer down mode entry command is used to enter deep power down mode. while the device is in deep power down mode, all internal circuits (except the cke buffer) are disabled in order to 10ua current consumption. deep power down mode exit command (cke = " h " du ring sdram in deep power down mode) this command is used to exit from deep power down mode. full initialization is required when the device exits from deep power down mode. data write enable /disable command (ldqm, udqm = " l/h " ) during a write cycle, the l dqm or udqm signal functions as data mask and can control every word of the input data. the ldqm signal controls dq0 to dq7 and udqm signal controls dq8 to dq15.
p relim inary w987x6cb publication release date: june 6, 2002 - 15 - revision a 1 read operation issuing the bank activate command to the idle bank puts it into the active stat e. when the read command is issued after t rcd from the bank activate command, the data is read out sequentially. the address inputs determine the starting column address for the burst. the initial read data becomes available after cas l atency from the issuing of the read command. the cas latency must be set in the mode register at power - up. when the precharge operation is performed on a bank during a burst read and operation, the burst operation is terminated. when t he read with auto precharge command is issued, the precharge operation is performed automatically after the read cycle, then the bank is switched to the idle state. this command cannot be interrupted by any other commands. refer to the diagrams for read o peration. write operation issuing the write command after t rcd from the bank activate command. the address inputs determine the starting column address. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the wr ite command is issued. the remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. data supplied to the dq pins after burst finishes will be ignored. the burst length of the write data (burst length) and addressing mode must be set in the mode register at power - up. when the precharge operation is performed in a bank during a burst write operation, the burst operation is terminated. when the write with auto precharge command is issued, the precharge op eration is performed automatically after the write cycle, then the bank is switched to the idle state, the write with auto precharge command cannot be interrupted by any other command for the entire burst data duration. precharge the precharge command is u sed to precharge or close a bank that has been activated. the precharge command is entered when cs, ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank separately or all banks simulta neously. three address bits, a10, bs0, and bs1, are used to define which bank(s) is to be precharged when the command is issued. after the precharge command is issued, the precharged bank must be reactivated before a new read or write access can be execute d. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (t rp ). burst termination when the precharge command is used for a bank in a burst cycle, the burst operation is terminated. when burst r ead cycle is interrupted by the precharge command, read operation is disabled after clock cycle of ( cas latency) from the precharge command. when the burst write cycle is interrupted by the precharge command . the input circuit is reset at the same clock cycle at which the precharge command is issued. in this case, the dqm signal must be asserted ?high? during t wr to prevent writing the invalided data to the cell array. when the burst read stop command is issued for the bank in a burst r ead cycle, the burst read operation is terminated. the burst read stop command is not supported during a write burst operation.
p reliminary w987x6cb - 16 - interruption read interrupted by a read a burst read may be interrupted by another read command. when the previous burst is int errupted, the remaining addresses are overridden by the new read address with the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command the is satisfied. read int errupted by a write to interrupt a burst read with a write command, dqm may be needed to place the dqs (output drivers) in a high impedance state to avoid data contention on the dq bus. if a read command will issue data on the first and second clocks cycle s of the write operation, dqm is needed to insure the dqs are tri - stated. after that point the write command will have control of the dq bus and dqm masking is no longer needed. write interrupted by a write a burst write may be interrupted before completio n of the burst by another write command. when the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. write interrupted by a read a read command will interrupt a burst write operation on the same clock cycle that the read command is activated. the dqs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. when the read command is activated, any residual data from the burst write cycle will be ignored. refresh operation two types of refresh operation can be performed on the device: auto refresh and self refresh. by repeating the auto refresh cycle, each bank in turn refreshed automatically. the refresh operation must be performed 4096 times (rows) within 64ms. the period between the auto refresh command and the next command is specified by t rc . the self refresh mode is entered by issuing the self refresh entry co mmand at the rising edge of the clock. all banks must be idle prior to issuing the self refresh entry command. once the command is registered, cke must be held low to keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control signals, except cke, are disabled. the clock is internally disabled during self refresh operation to save power. the device will exit self refresh operation after cke is returned high. a minimum delay time is required when the device exits self refresh operation and before the next command can be issued. this delay is equal to the t rc cycle time plus the self refresh exit time. if, during normal operation, auto refresh cycles are issued in bursts (as opposed to being evenly distributed ), a burst of 4,096 auto refresh cycles should be completed just prior to entering and just after exiting the self refresh mode.
p relim inary w987x6cb publication release date: june 6, 2002 - 17 - revision a 1 power down mode the power down mode is initiated by holding cke low. all of the receiver circuits except cke are gated off to reduce the power. the power down mode does not perform any refresh operations, therefore the device can not remain in power down mode longer than the refresh period (t ref ) of the device. mode register set operation the mode register is programmed by the m ode register set command (mrs/emrs) when all banks are in the idle state. the data to be set in the mode register is transferred using the address pins of a0 to a11 inputs. the combination of bs0, bs1 detains this cycle is mrs or emrs. mode register descr iption the mode register designates the operation mode for the read or write cycle. the register is divided into four fields; (1) burst length field sets the length of burst data (2) addressing mode selection bit to designate the column access sequence in a burst cycle (3) cas latency field sets the access time in clock cycle (4) single write mode selection bit to designate write operation in burst or single write. mode register definition a0 a1 a2 a3 a4 a5 a6 burst length addressing mode cas latency (test mode) a8 reserved a0 a7 a0 a9 a0 write mode a10 a0 a11 bs0 "0" "0" a0 a3 a0 addressing mode a0 0 a0 sequential a0 1 a0 interleave a0 a9 single write mode a0 0 a0 burst read and burst write a0 1 a0 burst read and single write a0 a0 a2 a1 a0 a0 0 0 0 a0 0 0 1 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 1 0 1 a0 1 1 0 a0 1 1 1 a0 burst length a0 sequential a0 interleave 1 a0 1 a0 2 a0 2 a0 4 a0 4 a0 8 a0 8 a0 reserved a0 reserved a0 full page a0 cas latency a0 reserved a0 reserved 2 a0 3 reserved a0 a6 a5 a4 a0 0 0 0 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 0 0 1 defines it is a mrs cycls reserved "0" "0" bs1 "0" "0"
p reliminary w987x6cb - 18 - address sequence of sequential mode a column access is performe d by incrementing the column address input to the device. the address is varied by the burst length as the following. addressing sequence of sequential mode data access address burst length data 0 n 2 words (address bits is a0) data 1 n + 1 no carried from a0 to a1 data 2 n + 2 4 words (address bit a0, a1) data 3 n + 3 not carried from a1 to a2 data 4 n + 4 data 5 n + 5 8 words(address bits a2, a1 and a0) data 6 n + 6 not carried from a2 to a3 data 7 n + 7 addressing sequence of interleave m ode a column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. address sequence for interleave mode data access address burst length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 2 words data 1 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a8 a7 a6 a5 a4 a3 a2 a1 a0 4 words data 3 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a8 a7 a6 a5 a4 a3 a2 a1 a0 8 words data 5 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 6 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a8 a7 a6 a5 a4 a3 a2 a1 a0
p relim inary w987x6cb publication release date: june 6, 2002 - 19 - revision a 1 simplified s tate diagram mode register set idle cbr refresh self refresh row active power down precharge power on active power down write write suspend writea writea suspend read suspend read reada suspend reada precharge mrs ref act cke cke cke cke cke cke cke cke cke cke self self exit cke cke write with read write auto precharge auto precharge read with write write read pre(precharge termination) pre(precharge termination) read bst bst pre manual input automatic sequence notes: mrs = mode register set ref = refresh act = active pre = precharge writea = write with auto precharge reada = read with auto precharge
p reliminary w987x6cb - 20 - 13. timing waveforms command input timing clk a0-a11 bs0, 1 v ih v il t cmh t cms t ch t cl t t t t t cks t ckh t ckh t cks t cks t ckh cs ras cas we cke t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah t ck
p relim inary w987x6cb publication release date: june 6, 2002 - 21 - revision a 1 timing waveforms, continued read timing read cas latency t ac t lz t ac t oh t hz t oh burst length read command clk cs ras cas we a0-a11 bs0, 1 dq valid data-out valid data-out
p reliminary w987x6cb - 22 - timing waveforms, continued control timing of input/output data t cmh t cms t cmh t cms t ds t dh t ds t dh t ds t dh t ds t dh valid data-out valid data-out valid data-out valid data-in valid data-in valid data-in valid data-in t ckh t cks t ckh t cks t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t cmh t cms t cmh t cms t oh t ac t oh t ac t oh t hz open t lz t ac t oh t ac t ckh t cks t ckh t cks t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out clk dqm dq0 -15 (word mask) (clock mask) clk cke dq0 -15 clk control timing of input data control timing of output data (output enable) (clock mask) dqm dq0 -15 cke clk dq0 -15
p relim inary w987x6cb publication release date: june 6, 2002 - 23 - revision a 1 timing waveforms, continued mode register set cycle a0 a1 a2 a3 a4 a5 a6 burst length addressing mode cas latency (test mode) a8 reserved a0 a7 a0 a9 a0 write mode a10 a0 a11 bs0 "0" "0" a0 a3 a0 addressing mode a0 0 a0 sequential a0 1 a0 interleave a0 a9 single write mode a0 0 a0 burst read and burst write a0 1 a0 burst read and single write a0 a0 a2 a1 a0 a0 0 0 0 a0 0 0 1 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 1 0 1 a0 1 1 0 a0 1 1 1 a0 burst length a0 sequential a0 interleave 1 a0 1 a0 2 a0 2 a0 4 a0 4 a0 8 a0 8 a0 reserved a0 reserved a0 full page a0 cas latency a0 reserved a0 reserved 2 a0 3 reserved a0 a6 a5 a4 a0 0 0 0 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 0 0 1 t rsc t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah clk cs ras cas we a0-a11 bs0,1 register set data next command a0 reserved "0" "0" bs1 "0" "0"
p reliminary w987x6cb - 24 - 14. operating timing example interleaved bank read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t rc t rc t ras t rp t ras t rp t rp t ras t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read precharge precharge precharge raa rbb rac rbd rae raa caw rbb cbx rac cay rbd cbz rae aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 bank #0 idle bank #1 bank #2 bank #3
p relim inary w987x6cb publication release date: june 6, 2002 - 25 - revision a 1 operating timing example, continued inte rleaved bank read (burst length = 4, cas latency = 3, auto precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t rc t ras t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read t rc raa rbb rac rbd rae dq aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 ap* ap* ap* raa caw rbb cbx rac cay rbd rae cbz
p reliminary w987x6cb - 26 - operating timing example, continued interleaved bank read (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t rc t rc t ras t rp t ras t rp t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 cz0 (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active read precharge active read precharge active t ac t ac read precharge t ac bank #0 idle bank #1 bank #2 bank #3
p relim inary w987x6cb publication release date: june 6, 2002 - 27 - revision a 1 operating timing example, continued interleaved bank read (burst length = 8, cas la tency = 3, auto precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t rc t ras t rp t ras t ras t rp t rcd t rcd t rcd t rrd t rrd ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 cz0 raa raa cax rbb rbb cby (clk = 100 mhz) rac rac caz * ap is the internal precharge start timing active read active active read t cac t cac t cac clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bank #0 idle bank #1 bank #2 bank #3 read ap* ap* bs0
p reliminary w987x6cb - 28 - operating timing example, continued interleaved bank write (burst length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 (clk = 100 mhz) write precharge active active write precharge active write clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 idle bank #0 bank #1 bank #2 bank #3 t ras
p relim inary w987x6cb publication release date: june 6, 2002 - 29 - revision a 1 operating timing example, continued interleaved bank write (burst length = 8, auto precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rab rac ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 caz (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active write write active bank #0 idle bank #1 bank #2 bank #3 ap* active write ap*
p reliminary w987x6cb - 30 - operating timing example, continued page mod e read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ccd t ccd t ccd t ras t rp t ras t rp t rcd t rcd t rrd raa raa cai rbb rbb cbx cay cam cbz a0 a1 a2 a3 bx0 bx1 ay0 ay1 ay2 am0 am1 am2 bz0 bz1 bz2 bz3 (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active read active read read read read precharge t ac t ac t ac t ac t ac bank #0 idle bank #1 bank #2 bank #3 ap*
p relim inary w987x6cb publication release date: june 6, 2002 - 31 - revision a 1 operating timing example, continued page mode read/write (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ras t rp t rcd t wr raa raa cax cay ax0 ax1 ax2 ax3 ax4 ax5 ay1 ay0 ay2 ay4 ay3 q q q q q q d d d d d (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs0 we cas ras cs bs1 active read write precharge t ac bank #0 idle bank #1 bank #2 bank #3
p reliminary w987x6cb - 32 - operating timing example, continued auto precharge read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t ras t rp t ras t rp t rcd t rcd t ac active read ap* active read raa rab raa caw rab cax aw0 aw1 aw2 aw3 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 t ac ap* bx0 bx1 bx2 bx3
p relim inary w987x6cb publication release date: june 6, 2002 - 33 - revision a 1 operating timing example, continued auto precharge write (burst length = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t ras t rp t ras t rp raa t rcd t rcd rab rac raa caw rab cax rac aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 active active write ap* active write ap* * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3
p reliminary w987x6cb - 34 - operating timing example, continued auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) all banks prechage auto refresh auto refresh (arbitrary cycle) t rc t rp t rc clk dq cke dqm a0-a9, a11 a10 we cas ras cs bs0,1
p relim inary w987x6cb publication release date: june 6, 2002 - 35 - revision a 1 operating timing example, continued self refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs0,1 we cas ras cs t cks t sb t cks t cks all banks precharge self refresh entry arbitrary cycle t rp self refresh cycle t rc no operation cycle
p reliminary w987x6cb - 36 - operating timing example, continued burst read and single write (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk cs ras cas we bs0 bs1 a10 a0-a9, a11 dqm cke dq (clk = 100 mhz) t rcd rba rba cbv cbw cbx cby cbz av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 q q q q d d d q q q q t ac t ac read read single write active bank #0 idle bank #1 bank #2 bank #3
p relim inary w987x6cb publication release date: june 6, 2002 - 37 - revision a 1 operating timing example, continued power down mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) raa caa raa cax raa raa ax0 ax1 ax2 ax3 t sb t cks t cks t cks t sb t cks active standby power down mode precharge standby power down mode active nop precharge nop active note: the powerdown mode is entered by asserting cke "low". all input/output buffers (except cke buffers) are turned off in the powerdown mode. when cke goes high, command input must be no operation at next clk rising edge. clk dq cke dqm a0-a9 a11 a10 bs we cas ras cs read
p reliminary w987x6cb - 38 - operating timing example, continued auto precharge timing (read cycle) read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read act q0 q3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note ) t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 (2) cas latency=3 t rp t rp t rp t rp
p relim inary w987x6cb publication release date: june 6, 2002 - 39 - revision a 1 operating timing example, continued auto precharge timing (write cyc le) write act ap 0 11 10 9 8 7 6 5 4 3 2 1 d0 d0 d0 d0 ap act d1 ap act d1 d1 d2 d2 d3 d3 d4 d5 d6 d7 ap act write write write (1) cas latency=2 write act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least tras (min). represents the write with auto precharge command. represents the start of internal precharging. represents the bank activate command. note ) t rp t wr t rp t wr t rp t wr t rp t wr ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq d0 ap act ap act d1 d0 ap act d1 d2 d3 ap act d0 d1 d2 d3 d4 d5 d6 d7 write write write write d0 (2) cas latency=3 t rp t wr t rp t wr t rp t wr t rp t wr ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
p reliminary w987x6cb - 40 - operating timing example, continued timing chart of read to write cycle note: the output data must be masked by dqm to avoid i/o conflict 11 10 9 8 7 6 5 4 3 2 1 0 (1) cas latency=2 in the case of burst length = 4 read read write write dq dq ( b ) command dqm dqm d0 d1 d2 d3 d0 d1 d2 d3 ( a ) command (2) cas latency=3 read write read write d0 d1 d2 d3 ( a ) command dq dq dqm ( b ) command dqm d0 d1 d2 d3 timing chart of write to read cycle read write 0 11 10 9 8 7 6 5 4 3 2 1 q0 read q1 q2 q3 read read write write q0 q1 q2 q3 write q0 q1 q2 q3 d0 d1 dq dq ( a ) command dq dq dqm ( b ) command dqm ( a ) command ( b ) command dqm dqm in the case of burst length=4 (1) cas latency=2 (2) cas latency=3 d0 d0 d1 q0 q1 q2 q3 d0
p relim inary w987x6cb publication release date: june 6, 2002 - 41 - revision a 1 operating timing example, continued timing chart of burst stop cycle (burst stop command) read bst 0 11 10 9 8 7 6 5 4 3 2 1 dq q0 q1 q2 q3 bst ( a ) cas latency =2 command ( b )cas latency = 3 (1) read cycle q4 (2) write cycle command read command q0 q1 q2 q3 q4 q0 q1 q2 q3 q4 dq dq write bst note: represents the burst stop command bst timing chart of burst stop cycle (precharge command) in the case of burst lenght = 8 read prcg 0 11 10 9 8 7 6 5 4 3 2 1 q0 q1 q2 q3 q0 q1 q2 q3 read prcg q4 q4 ( a )cas latency =2 command ( b )cas latency = 3 command dq dq dq ( b )cas latency = 3 command (1) read cycle (2) write cycle write write prcg prcg ( a ) cas latency =2 command dqm dqm t wr t wr d0 d1 d2 d3 d4 dq d0 d1 d2 d3 d4 dq
p reliminary w987x6cb - 42 - operating timing example, continued cke/dqm input timing (write cycle) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk clk
p relim inary w987x6cb publication release date: june 6, 2002 - 43 - revision a 1 operating timing example, continued cke/dqm input timing (read cycle) 7 6 5 4 3 2 1 ( 1 ) q1 q6 q4 q3 q2 clk cycle no. external internal cke dqm dq open open 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q1 q6 q2 clk cycle no. external internal cke dqm dq q5 q4 ( 3 ) q4 clk clk clk q3
p reliminary w987x6cb - 44 - operating timing example, continued self refresh/power down mode exit t iming asynchronous control input buffer turn on time ( power down mode exit time ) is specified by tcks(min) + tck(min) command nop clk cke command a ) t ck < t cks (min)+t ck (min) input buffer enable command clk cke command b) t ck >= t cks (min) + t ck (min) input buffer enable note ) command nop all input buffer(include clk buffer) are turned off in the power down mode and self refresh mode represents the no-operation command represents one command t ck t ck t cks (min) +t ck (min) t cks (min) +t ck (min)
p reliminary w987x6cb publication release date: june 6, 2002 - 45 - revision a 1 15. package dimension fbga 54 balls (8 x 9 x 1.2 mm^3, f = 0.40 mm)
p reliminary w987x6cb - 46 - 16. revision history version date page description a 1 june 6, 2002 - initial issued headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu chiu, taipei, 114, taiwan, r.o.c.

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